#Pin LOC constraints for the status signals init_calib_complete and data_compare_error

#LOC constraints provided if the pins are selected for status signals

set_property PACKAGE_PIN W8 [ get_ports "c0_data_compare_error" ]
set_property IOSTANDARD LVCMOS18 [ get_ports "c0_data_compare_error" ]

set_property PACKAGE_PIN Y8 [ get_ports "c0_init_calib_complete" ]
set_property IOSTANDARD LVCMOS18 [ get_ports "c0_init_calib_complete" ]

set_property PACKAGE_PIN AF6 [ get_ports "c0_sys_clk_n" ]
set_property IOSTANDARD DIFF_SSTL12 [ get_ports "c0_sys_clk_n" ]

set_property PACKAGE_PIN AF7 [ get_ports "c0_sys_clk_p" ]
set_property IOSTANDARD DIFF_SSTL12 [ get_ports "c0_sys_clk_p" ]

set_property PACKAGE_PIN U9 [ get_ports "sys_rst" ]
set_property IOSTANDARD LVCMOS18 [ get_ports "sys_rst" ]

set_property PACKAGE_PIN AB1 [ get_ports "c0_ddr4_bg[0]" ]
set_property PACKAGE_PIN AB2 [ get_ports "c0_ddr4_ba[0]" ]
set_property PACKAGE_PIN AB3 [ get_ports "c0_ddr4_adr[14]" ]
set_property PACKAGE_PIN AB4 [ get_ports "c0_ddr4_adr[13]" ]
set_property PACKAGE_PIN AB5 [ get_ports "c0_ddr4_cke[0]" ]
set_property PACKAGE_PIN AB6 [ get_ports "c0_ddr4_dq[6]" ]
set_property PACKAGE_PIN AB7 [ get_ports "c0_ddr4_dq[4]" ]
set_property PACKAGE_PIN AB8 [ get_ports "c0_ddr4_dq[2]" ]
set_property PACKAGE_PIN AC1 [ get_ports "c0_ddr4_cs_n[0]" ]
set_property PACKAGE_PIN AC2 [ get_ports "c0_ddr4_ba[1]" ]
set_property PACKAGE_PIN AC3 [ get_ports "c0_ddr4_adr[12]" ]
set_property PACKAGE_PIN AC4 [ get_ports "c0_ddr4_adr[11]" ]
set_property PACKAGE_PIN AC6 [ get_ports "c0_ddr4_dq[7]" ]
set_property PACKAGE_PIN AC7 [ get_ports "c0_ddr4_dq[5]" ]
set_property PACKAGE_PIN AC8 [ get_ports "c0_ddr4_dq[3]" ]
set_property PACKAGE_PIN AC9 [ get_ports "c0_ddr4_dm_dbi_n[0]" ]
set_property PACKAGE_PIN AD1 [ get_ports "c0_ddr4_adr[16]" ]
set_property PACKAGE_PIN AD2 [ get_ports "c0_ddr4_adr[15]" ]
set_property PACKAGE_PIN AD4 [ get_ports "c0_ddr4_adr[10]" ]
set_property PACKAGE_PIN AD5 [ get_ports "c0_ddr4_adr[9]" ]
set_property PACKAGE_PIN AD7 [ get_ports "c0_ddr4_dqs_t[0]" ]
set_property PACKAGE_PIN AD9 [ get_ports "c0_ddr4_odt[0]" ]
set_property PACKAGE_PIN AE2 [ get_ports "c0_ddr4_dqs_t[1]" ]
set_property PACKAGE_PIN AE3 [ get_ports "c0_ddr4_dq[10]" ]
set_property PACKAGE_PIN AE4 [ get_ports "c0_ddr4_reset_n" ]
set_property PACKAGE_PIN AE5 [ get_ports "c0_ddr4_adr[6]" ]
set_property PACKAGE_PIN AE7 [ get_ports "c0_ddr4_dqs_c[0]" ]
set_property PACKAGE_PIN AE8 [ get_ports "c0_ddr4_dq[1]" ]
set_property PACKAGE_PIN AE9 [ get_ports "c0_ddr4_dq[0]" ]
set_property PACKAGE_PIN AF1 [ get_ports "c0_ddr4_dq[14]" ]
set_property PACKAGE_PIN AF2 [ get_ports "c0_ddr4_dqs_c[1]" ]
set_property PACKAGE_PIN AF3 [ get_ports "c0_ddr4_dq[11]" ]
set_property PACKAGE_PIN AF5 [ get_ports "c0_ddr4_adr[7]" ]
set_property PACKAGE_PIN AF8 [ get_ports "c0_ddr4_adr[2]" ]
set_property PACKAGE_PIN AG1 [ get_ports "c0_ddr4_dq[15]" ]
set_property PACKAGE_PIN AG3 [ get_ports "c0_ddr4_dq[8]" ]
set_property PACKAGE_PIN AG4 [ get_ports "c0_ddr4_dm_dbi_n[1]" ]
set_property PACKAGE_PIN AG5 [ get_ports "c0_ddr4_ck_c[0]" ]
set_property PACKAGE_PIN AG6 [ get_ports "c0_ddr4_ck_t[0]" ]
set_property PACKAGE_PIN AG8 [ get_ports "c0_ddr4_adr[3]" ]
set_property PACKAGE_PIN AG9 [ get_ports "c0_ddr4_adr[0]" ]
set_property PACKAGE_PIN AH1 [ get_ports "c0_ddr4_dq[13]" ]
set_property PACKAGE_PIN AH2 [ get_ports "c0_ddr4_dq[12]" ]
set_property PACKAGE_PIN AH3 [ get_ports "c0_ddr4_dq[9]" ]
set_property PACKAGE_PIN AH4 [ get_ports "c0_ddr4_act_n" ]
set_property PACKAGE_PIN AH6 [ get_ports "c0_ddr4_adr[8]" ]
set_property PACKAGE_PIN AH7 [ get_ports "c0_ddr4_adr[5]" ]
set_property PACKAGE_PIN AH8 [ get_ports "c0_ddr4_adr[4]" ]
set_property PACKAGE_PIN AH9 [ get_ports "c0_ddr4_adr[1]" ]


create_waiver -internal -user ddr4_v2_2_23 -scope -type METHODOLOGY -id {TIMING-17} -description "Ignore the TIMING-17 Critical Warning for sl_iport_i" -objects [get_pins -quiet -leaf -of [get_nets -quiet u_ddr4_*/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i*] -filter {DIRECTION==IN}]
